1. Field of the Invention
The present invention is directed to a semiconductor device, and in particular, to a synchronous dynamic random access memory (SDRAM) of a semiconductor memory.
2. Background of the Related Art
When a defect is found in any of numerous cells in a memory, the memory is classified inferior and not used. As the integration of the memory is increased, the likelihood of a defect generated in a few cells is high. In this case, to classify and not use an entire memory as inferior is an inefficient method that lowers yield. Therefore, when the defect is generated in the memory cell, a related art method of increasing the yield substitutes a spare cell provided in the memory for a defective cell.
For a highly integrated memory, a merged bank architecture MBA reduces chip size by dividing the memory into more than four banks and shares an X-address predecoder or a control block among the respective banks.
FIG. 1 is a block diagram illustrating a related art refresh scheme for redundant word lines in a memory. A core array 10 is a first bank architecture including a plurality of memory blocks BK0-BKn that are distinguished from one another by upper and lower bit line sense amplifiers BLSA. Each of the respective memory blocks BK0-BKn has normal word lines NWL and redundant word lines RWL.
A fuse read only memory (ROM) array 20 includes a plurality of fuse ROMs. The plurality of the fuse ROMs are equal in number to the memory blocks BK0-BKn. The respective fuse ROMs are programmed with address information regarding the redundant word lines to repair.
A refresh counter 30 serves to sequentially generate an internal address during a refresh operation. A comparator 40 sequentially compares an external address with the address information programmed in the fuse ROM array 20 during a normal operation. The comparator 40 sequentially compares the address information programmed in the fuse ROM array 20 with the internal address outputted from the refresh counter 30 during a refresh operation. When two addresses are hit, a redundant word line enable signal RWEN is activated. On the other hand, when the two addresses are missed, a normal word line enable signal NWEN is activated.
An X-address predecoder 50 outputs an upper coding signal that is a memory block selecting signal and a lower coding signal that is a word line selecting signal by decoding the external address (X-address) during the normal operation and decoding the internal address that is outputted from the refresh counter 30 during the refresh operation. For instance, a 16M data random access memory (DRAM), the X-address predecoder 50 uses addresses A8.about.A11 to of the external addresses A0.about.A11 to select one memory block from the plurality of memory blocks BK0-BKn. The X-address predecoder uses the other addresses A0.about.A7 to select one word line from 256 word lines in a selected memory block.
Row decoder and word line drivers 60-1.about.60-n are operated by the normal word line enable signal NWEN from the comparator 40. Pursuant to the upper coding signal outputted from the X-address predecoder 50, the row decoder and word line drivers 60-1.about.60-n select one memory block from the plurality of memory blocks BK0-BKn by enabling the bit line sense amplifiers BLSA. In accordance with the lower coding signal outputted from the X-address predecoder 50, the row decoder and word line drivers 60-1.about.60-n drive one word line of the 256 word lines in the selected block.
Redundant row decoder and word line drivers 61-1.about.61-n are operated by the redundant word line enable signal RWEN from the comparator 40. Pursuant to the lower coding signal that is outputted from the X-address predecoder 50, the redundant row decoder and word line drivers 61-1.about.61-n drive a corresponding redundant word line RWL in the selected block.
The operation of the related art refresh scheme for redundant word lines in the memory will now be described. During the normal operation of the memory, the X-address predecoder 50 outputs the upper coding signal and the lower coding signal by decoding the external address (X-address). The comparator 40 sequentially compares the inputted external address with the address information programmed in the fuse ROM array 20. When two addresses are the same (e.g., hit), the redundant word line enable signal RWEN is active. When the two addresses are missed, the comparator 40 makes the normal word line enable signal NWEN active.
When the normal word line enable signal NWEN is active in the comparator 40, the plurality of row decoders and word line drivers 60-1.about.60-n are operated. In accordance with the upper coding signal outputted from the X-address predecoder 50, the operated row decoders and word line drivers 60-1.about.60-n enable the corresponding bit line sense amplifiers BLSA and select one memory block from the plurality of memory blocks BK0-BKn, for example, the memory block BK0. At the same time, pursuant to the lower coding signal outputted from the X-address predecoder 50, a corresponding one of the row decoder and word line drivers 60-1-.about.0-n drive one normal word line of the 256 normal word lines in the selected memory block BK0.
During this operation, when the external address and the address information programmed in the fuse ROM array 20 are equal (e.g. hit) the redundant word line enable signal RWEN is activated from the comparator 40. The row decoder and word line driver 60-1 is disabled and the redundant row decoder and word line driver 61-1 is enabled.
Therefore, in accordance with the lower coding signal outputted from the X-address predecoder 50, the redundant row decoder and word line driver 61-1 drives the redundant word line RWL in the selected memory block BK0. In this manner, the normal word line NWL is replaced by the redundant word line RWL in the memory block BK0.
That is, during the normal operation, the external address and the address information programmed in the fuse ROM array 20 are missed to activate the normal word line enable signal NWEN and drive the normal word line NWL. On the other hand, when the two addresses are hit to activate the redundant word line enable signal RWEN, the redundant word line RWL is driven. Accordingly, when the defect is generated in any of the memory cells, the inferior cell can be avoided or repaired by replacing the normal word line NWL with the redundant word line RWL.
The refresh operation of the related art refresh scheme of the memory in FIG. 1 will now be described. In accordance with a refresh signal, the refresh counter 30 sequentially generates the internal address and provides it to the comparator 40. The X-address predecoder 50 outputs the upper coding signal and the lower coding signal by decoding the internal address from the refresh counter 30.
At this time, the comparator 40 sequentially compares the inputted internal address with the address information programmed in the fuse ROM array 20. When the two addresses are the same, the redundant word line enable signal RWEN is activated. On the other hand, when the two addresses are different, the normal word line enable signal NWEN is activated .
The X-address predecoder 50 outputs the upper coding signal and the lower coding, signal by decoding the internal address inputted from the refresh counter 30. As described above, the plurality of row decoder and word line drivers 60-1.about.60-n are enabled by the normal word line enable signal NWEN. Then, pursuant to the upper coding signal outputted from the X-address predecoder 50, the row decoder and word line drivers 60-1.about.60-n select one memory block from the plurality of memory blocks BKO-BKn. Pursuant to the lower coding signal, the row decoder and word line drivers 60-1.about.60-n carry out the refresh operation in the selected memory block, for example, the memory block BK0, by sequentially driving the normal word lines NWL.
In addition, when the internal address is equal to the address information in the fuse ROM array 20, the redundant row decoder and word line driver 61-1 is enabled by the redundant word line enable signal RWEN. Then, pursuant to the lower coding signal outputted from the X-address predecoder 50, the redundant row decoder and word line driver 61-1 performs the refresh operation by driving the redundant word line RWL In the selected memory block.
Namely, during the refresh operation, when internal address and the address information programmed in the fuse ROM array 20 are different to activate the normal word line enable signal NWEN, the refresh operation is carried out by driving the normal word line. On the other hand, when the two addresses are equal to activate the redundant word line enable signal RWEN, the refresh operation is performed by driving the redundant word line RWL.
As described above, the related art refresh scheme has various disadvantages. The related art refresh scheme for the redundant word lines has a disadvantage in that a repair of the redundant word line can be carried out solely within an identical memory block, which results in the reduction of efficiency of the redundant word line or the fuse.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.